The present invention relates to the field of image processing. More specifically, the present invention relates to encoding and decoding digital video data.
The Digital Video (DV) format is quickly becoming the standard for many digital video applications, including consumer electronic video devices. For example, DV format camcorders can now be found with more frequency and at more competitive prices than the conventional analog 8 mm and VHS camcorders. At the same time, DV camcorders provide advantages which are inherent to digital technology, such as high quality of video and sound, digital filtering, digital error correction, and the like. DV provides quality at or higher than the high-end of the conventional analog camcorders such as Hi-8 mm and S-VHS, with much added flexibility. Also, digital format data can be repeatedly copied without loss of quality.
Digital video applications generally involve first encoding and then decoding video data. Encoded digital video constitutes a very long sequential combination, or bitstream, of zeroes and ones. The bitstream is stored for later processing, including ultimate decoding. To store the bitstream, data in sets of 16 bits are commonly packed as words. Decoding such words can be an involved process raising many challenges. One challenge in standard digital video applications is to decode efficiently and accurately. Efficient and accurate decoding, however, can be difficult to implement because the data is stored as words during the encoding process in a way that distorts the original sequence of the data.
Recursive operations in the decoding process are often complicated by such distortion. Recursive operations are generally characterized by subsequent results depending on earlier results. In the context of digital video applications, recursive operations often entail decoding data on a word-by-word basis to detect valid code words. That is, a first code word is decoded, and the start and the end of the first code word is identified. Based on the end of the first code word, the start of a second valid code word is identified. The second code word is then decoded, and the end of the second word is identified. The process repeats, continuing for subsequent code words.
The data in standard DV applications is stored according to conventions that often require separation of the bits that constitute a code word. Accordingly, the ability to detect a code word by identifying the start and end of the code word is often unduly complex. Because of the recursive nature of decoding, problems associated with decoding a particular code word apply not only to that code word, but also for all subsequent code words in the bitstream. Such problems can render parallel decoding execution infeasible. Additionally, circuits for implementing a parallel decoding scheme can suffer from excessive gate counts.
What is therefore required is decoding methods and apparatus that provides fast and efficient concatenation of bits to form code words. The implementation of such a method and apparatus should support the concatenation of words having bits that are not easily identified or properly justified, on a word-to-word basis. Preferably, the implementation should also be relatively small in required size when implemented in an integrated circuit. Finally, the implementation should provide an acceptable level of computational accuracy and, consequently, image quality.
The present invention solves the problems associated with the prior art by providing methods and apparatus for efficiently and accurately concatenating odd-length words.
In accordance with one of many aspects of the present invention, a start bit value and a remaining bit value are initialized. Selected bits from a first concatenation of words are identified based on the start bit value and the remaining bit value. Detection of a first valid code word having a first code word length is attempted from the selected bits.
In accordance with other aspects of the present invention, the start bit value and the remaining bit value are altered based on the first code word length if the first valid code word is detected.
In accordance with further aspects of the present invention, a first word and a second word are combined in the first concatenation. The second word is sequentially associated with the first word in a bitstream.
In accordance with still other aspects of the present invention, the first word is from an unfinished block. The second word is from a finished block.
In accordance with still further aspects of the present invention, the first word is stored in a scratch memory. The second word is stored in the scratch memory.
In accordance with still other aspects of the present invention, the second word is aligned in the scratch memory.
In accordance with still further aspects of the present invention, a second concatenation involving a third word is performed. The third word is sequentially associated with the second word in the bitstream.
In accordance with still other aspects of the present invention, a memory includes finished blocks and unfinished blocks. If data corresponding to a block can be stored entirely in the block, the block is referred to as a xe2x80x9cfinished blockxe2x80x9d. If the data for a block exceeds the capacity of the block so that the data cannot be stored entirely in the block, the block is referred to as an xe2x80x9cunfinished blockxe2x80x9d. A first word and a second word, either from a finished block or an unfinished block, are sequentially associated. The first word and the second word are concatenated. A start bit value and a remaining bit value are initialized and used to detect a valid code word in the concatenation. If a valid code word is detected, the start bit value and the remaining bit value are altered by the length of the valid code word. The valid code word in the concatenation is discarded. Detection of another valid code word is attempted using the starting bit value and the remaining bit value as altered. If no valid code word is found, another word from the memory is concatenated with the remaining portion of the earlier concatenation and detection of another valid code word is attempted. This process repeats until all desired valid code words are detected.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.